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ECE411

ECE 411 (Computer Organization and Design) is a 4-credit-hour course that can be used to fulfill both a design elective and an advanced computing elective for CE students and counts as a technical elective for EE students.

Content Covered

  • Introduction and review of logic design
  • Instruction set architectures
  • Computer arithmetic
  • Control unit design
  • Memory organization: memory technologies, memory performance evaluation, interleaved memory, associative memory, virtual memory organization, cache memory
  • Input-Output: devices, controllers, busy wait I/O, channels, interrupts, direct memory access to multiport memory
  • Reliability and performance evaluation
  • Introduction to parallel processing, case studies

This course expands upon what is taught in ECE385. In ECE385, you learn how to make a processor work. In ECE411, you learn how to optimize a processor's performance. You'll learn about pipelining, the idea of dividing an instruction into multiple steps and simultaneously executing multiple instructions at once by overlapping the stages. You'll also learn about speculation, which is guessing what instruction the processor will do next, allowing the processor to execute the instruction early while simultaneously leaving the processor a few steps ahead if guessed correctly. You'll also learn about cache, a type of memory which is closer to the processor and hence provides lower latency for memory access, as well as learn about different types of memory/storage. In addition to the core features in a computer, the class also touches upon how to evaluate processor performance, including metrics like power and area, and also even gives insight into emerging topics like parallel processing and even accelerator architectures.

Prerequisites

Although ECE391 is the official prereq, only topics on virtual memory and I/O are needed and re-covered in ECE411 lectures anyways. The real prereq is ECE385, as it teaches SystemVerilog, which is used in all of the MPs for this course, so it is imperative to know how to write HDL before starting this course.

When to Take It

If you are looking to get an internship in the field of digital design (hardware), take this course ASAP after taking ECE385. Many interviewers at top hardware companies like Apple, NVIDIA, Qualcomm, etc will ask you technical questions relating to the content covered in this class. Make sure that when you take this class you don't take too many technical electives alongside it because it is very time-consuming and conceptually difficult.

Course Structure

The coursework is entirely MP-based. The class begins with MP0, which is just helps you setup your ECE411 environment on EWS and introduces you to the Synopsys tools (which are actaully industry-standard tools in digital design) that are used throughout the other MPs.

In MP1, you are tasked to verify a multiplier, FIFO, and CAM using UVM, an OOP-based verification methodology that's also used in the industry. You are also tasked to "reverse-engineer" a cacheline adaptor - you basically implement a cacheline adaptor to pass the tests which are already given to you. This MP focuses on giving you exposure to SystemVerilog as both an HDL and HVL.

In MP2, you are tasked to implement a processor using the RISC-V ISA. It's very similar to lab 5 of ECE385, except the ISA is entirely different. Like lab 5 of ECE385, this MP is divided into two checkpoints, and by the end of both checkpoints of this MP, you will have implemented all RV32I instructions with the exception of the FENCE, ECALL, EBREAK, and CSRR instructions. Note that this MP is a precursor to MP4, which will have you convert the processor into a pipelined processor.

In MP3, you are tasked to implement a two-way, set-associative cache to boost the performance of the processor you made in MP2. You'll learn about how reads and writes to cache differ from reads and writes to physical memory and what makes having a cache so advantageous to a processor's performance.

Finally, by the time you finish MP3, you'll have reached the halfway mark of the course, and begin work on MP4. In MP4, you work in groups of 3 and are assigned a TA mentor for your group, who will be your helping hand in formulating a design for a 5-stage pipelined RISC-V processor or an OoO Tomasulo's processor. From there, the checkpoints differ depending on what your group decides to do. For the 5-stage pipeline, it is easier to implement additional features, but you'll definitely learn even more if your group chooses to tackle the harder challenge of implementing an OoO processor based on Tomasulo's algorithm. After making that choice, the checkpoints differ, and even for other groups doing the same type of processor, the designs differ a lot, which is why your group is assigned a mentor TA. So lean on your mentor TA when you need help - that's what they're there for.

Instructors

In recent semesters, a rotation of three professors have taught the course. Professor Rakesh Kumar, Nam Sung Kim, and Jian Huang have all taught the course in recent semesters.

The course has changed to have professors handling the lecture component and the TAs handling the lab component.

Course Tips

Start on the MPs as soon as you get them. You only get one free extension that can be used on MPs 1-3, so if it really comes down to it, do your best to finish MP 1, 2, and at least checkpoint 1 of MP3. But of course, try to finish all 3 MPs, and it's especially important to finish MP3 because that way you'll be able to use the cache you designed in MP4.

Life After

If you enjoyed learning about computer architecture in ECE 411, you're just about ready to start applying for hardware internships at top companies like Apple, Qualcomm, Intel, AMD, and NVIDIA. And as of recently, notable software companies like Meta, Google, Microsoft, and even Amazon have started designing their own hardware. Besides these companies, there are ASIC or FPGA roles in many other companies that you can also apply to after taking this class. If you enjoyed learning about digital circuitry, you might consider ECE425 (Intro to VLSI System Design), which gives a more in-depth understanding into the electrical layout of chips like those you design in 411. Many of the courses building on 411 are grad courses, like ECE511 - Computer Architecture, ECE512 - Computer Microarchitecture, ECE522 - Emerging Memory and Storage Systems, ECE527 - SoC Design, and CS533 - Parallel Computer Architecture but a new ECE 498 has been introduced thanks to Professor Patel. In ECE498SJP - Accelerator Architectures, you design a hardware accelerator of your choice with a group you select as a semester-long project.

Infamous Topics

  • Pipelining: it is the basis of MP4, so you'll want to make sure you have a solid understanding of it and the issues that may arise while implementing your design.
  • Cache: used in MP3 and subsequently in MP4, it is also important to wrap your head around this, as it will ultimately also help you in your quest to build the best processor for the MP4 competition.

Resources

  • Recommended Text 1: Patterson & Hennessy: Computer Organization and Design (5th ed)
  • Recommended Text 2: Hennessy & Patterson: Computer Architecture: A Quantitative Approach (6th ed.)