ECE425
ECE425 (Intro to VLSI System Design) is a 3-credit-hour course that satisfies the Technical Elective requirements for ECE majors and satisfies the Advanced Computing Elective requirements for CEs. It is offered only in the spring semester.
Content Covered
The course begins by covering MOSFETs, including the derivtion of IV equations in various modes of operation and nonideal effects. It then covers transistor level implementations of common combinational and sequential logic and memory circuits as well as timing models, including Elmore Delay and Logical Effort. The last third of the course covers VLSI-related topics such as the VLSI workflow and associated tools used, Design for Test, PNR algorithms, and High-Level Synthesis. In parallel to the lectures, the MPs teach circuit design and layout using software such as Cadence Virtuoso.
Prerequisites
ECE385 is listed as the official prerequisite. The course expects a basic understanding of digital circuits and design concepts. A good knowledge of ECE120 and ECE385 is needed for this. Some knowledge or internship experience in digital circuit design is helpful in understanding cell placement and routing techniques discussed in the later part of the course. If you did well in 120 and 385 then you should not be at any disadvantage. Some of the later MPs require being able to understand and write SystemVerilog, for which ECE385 is required. ECE340 and ECE342 can also help with undertsanding MOSFETs at the beginning of the course. Many of the students who take this course last studied MOSFETS in ECE110, which heavily simplifies the topic. However, prior knowledge of MOSFETs is not needed and many students do well without it.
When to Take It
The course is only offered in the spring, so you should take it as soon as you finish the prerequisites. If you are considering a career in IC or processor design, this course will greatly help you understand layout challenges and algorithms. The course is complemented by ECE482 (Digital IC Design). ECE 425 focuses on a higher level of design and cell placement, while 482 focuses on a lower level such as gate delays and transistor level design. There is some overlap in content, especially with layout techniques and software tools. Therefore students taking both courses will have a significant advantage in both courses, especially using Cadence design software to do custom layouts.
Course Structure
The majority of the course is spent on the machine problems. There are four MPs. MP_intro teaches students the basics of schematic design, simulation, and layout in Cadence Virtuoso, an industry-standard software, by creating an inverter and buffer. The next MP, MP_stdcells, has students build a standard cell library of basic gates including NAND, NOR, MUX, and DFF using digital design and sizing concepts taught in lecture . The third MP, MP_datapath, is the most involved by far requiring around 40-50 hours over 5 weeks, where students design a RISCV32 microprocessor datapath. The cell library from MP1 and extra SystemVerilog code is used to create the schematic of the design in Cadence Virtuoso. The design is also simulated for verification. For the second-half of the MP, the design is laid out by hand to match the schematic in Cadence. The last MP, MP_pnr, introduces students to the automated pnr design flow using Synopsys Design Compiler and Cadence Innovus. A gate-level netlist of the processor control unit and of the entire CPU is generated from SystemVerilog code and the MP_stdcells standard cell library using Design Compiler, and a layout is automatically generated from it using Innovus. The third MP requires much less time than the second.
There are two midterms in the course and a final. They focus on the four homework assignments given throughout the course. A student will do well on exams if they have a good knowledge of the homework concepts. The exams and homework do not require a significant time commitment compared to the MPs; the time to do manual layout makes the MPs, especially MP_datapath, time consuming.
Instructors
Since Spring 2024, this course has been taught by professor Dong Kai Wang every spring semester.
Course Tips
The MPs for this course take a significant amount of time, so start early and go to office hours. Most students don't enter with prior Virtuoso experience, and the software can take some time to get used to and become proficient with.
Life After
This class is absolutely necessary if you plan on doing digital circuit design or processor design. Because designing to minimize timing, power, and area is critical in the modern age, VLSI knowledge is more important than ever. The MPs introduce you to the electronic chip design flow and use the exact Cadence and Synopsis software that is used in industry. You will have a huge advantage in interviews toward VLSI or physical design jobs if you have experience using these tools. Also knowing how transistors are placed in a layout is helpful for anyone doing digital or processor design, no matter what stage of the design flow you work on. If you plan on doing any level of physical design or advanced circuit design after HDL synthesis, this course and supplemental course material is practically a minimum requirement to seeking a comfortable internship/full-time job.
This course is also a hard prerequisite for ECE427/498HK, Advanced VLSI System Design (the "tapeout" course), where seniors/grad students design their own digital/analog chip using design automation tools to perform layout, integration, and verification of the chip in a semester-long design project. The chip is then fabbed by TSMC and students spend the next semester doing bringup on the chip.