ECE425
ECE425 (Intro to VLSI System Design) is a 3-credit-hour course that satisfies the Technical Elective requirements for ECE majors and satisfies the Advanced Computing Elective requirements for CEs. It is offered only in the spring semester.
Content Covered
The course begins with a review of ECE385 concepts, such as finite state machines and flip flops. It then covers transistor level implementations of common logic circuits. Layout design rules and best practices are discussed, with MPs giving students a chance to learn the impact of these rules. The second half of the course covers VLSI chip placement and routing techniques. Much of IC design is focused on minimizing area, and the course provides a history of the algorithms done to do so. Important VLSI concepts such as routing, cell placement, and partitioning are also discussed. The benefits and drawbacks of each algorithm are highlighted. Much of the discussion focuses on the high-level algorithms used by software tools to place transistors and logic gates.
Prerequisites
ECE385 is listed as the official prerequisite. The course begins with basic digital design concepts and how circuits are implemented in practice. A good knowledge of ECE120 and 385 are needed for this. Some knowledge or internship experience in digital circuit design is helpful in understanding cell placement and routing techniques discussed in the later part of the course. If you did well in 120 and 385 then you should not be at any disadvantage. Some students took this course concurrently with ECE385; they did not feel they lacked knowledge for the course at any time other than writing Verilog code for the second MP before Verilog was introduced in ECE385, which could be learned fairly quickly.
When to Take It
The course is only offered in the spring, so you should take it as soon as you finish the prerequisites. If you are considering a career in IC or processor design, this course will greatly help you understand layout challenges and algorithms. The course is complemented by ECE482 (Digital IC Design). ECE 425 focuses on a higher level of design and cell placement, while 482 focuses on a lower level such as gate delays and transistor level design. There is some overlap in content, especially with layout techniques and software tools. Therefore students taking both courses will have a significant advantage in both courses, especially using Cadence design software to do custom layouts.
Course Structure
The majority of the course is spent on the machine problems. There are three MPs. In the first one students build a standard cell library of basic gates such as AND, OR, NOT and use them to create a very simple system, such as an 8-bit full adder. The second MP is the most involved by far requiring around 5-10 hours a week consistently for about a month, where students design of the AMD 2901 microprocessor datapath. The cell library from MP1 and extra Verilog RTL code is used to create the schematic of the design in Cadence Virtuoso. You then test and debug your design, trying to reduce the number of transistors as much as possible. For the second-half of the MP, the design is laid out by hand to match the schematic in Cadence Layout. The third MP introduces students to the automated design flow using Synopsys Design Compiler and Cadence Encounter. A gate-level schematic of the processor control unit is generated from Verilog RTL code and a layout is automatically generated from the Verilog with a professional standard-cell library. The third MP requires much less time than the second.
There are two midterms in the course and a final. They focus on the four or five homework assignments given throughout the course. A student will do well on exams if they have a good knowledge of the homework concepts. The exams and homework do not require a significant time commitment compared to the MPs; the time to manually hand-draw the circuit layout makes the MPs time consuming.
Instructors
In the past spring semesters before Spring 2024, the course has been traditionally taught by Professor Anu Aggarwal. As of Spring 2024, it was taught by the new professor Dong Kai Wang, and it will likely continue to be taught by him for future spring semesters. The course has drastically changed since he took over, so if you want a more recent insight into the course, reach out to current ECE seniors/grad students specializing in computer architecture and/or digital design.
Life After
This class is absolutely necessary if you plan on doing digital circuit design or processor design. Because designing to minimize timing, power, and area is critical in the modern age, VLSI knowledge is more important than ever. The MPs introduce you to the electronic chip design flow and use the exact Cadence and Synopsis software that is used in industry. You will have a huge advantage in interviews toward VLSI or physical design jobs if you have experience using these tools. Also knowing how transistors are placed in a layout is helpful for anyone doing digital or processor design, no matter what stage of the design flow you work on. If you plan on doing any level of physical design or advanced circuit design after HDL synthesis, this course and supplemental course material is practically a minimum requirement to seeking a comfortable internship/full-time job.
The course is a prerequisite to a graduate level VLSI course, ECE 582 Physical VLSI Design. It provides a more advanced look at the concepts introduced in 425. It is also a hard prerequisite to ECE498HK, Advanced VLSI System Design, where seniors/grad students design their own digital/analog chip using design automation tools to perform layout, integration, and verification of the chip in a semester-long design project.